In the latest version of AIDA64, Preliminary info for AMD’s upcoming 7nm Zen 2 based, 3rd Gen Ryzen Threadripper ‘Castle Peak’ high-end desktop and EPYC Rome server processors has been added.
The company is expected to launch them at the Computex 2019, next month and AMD’s EPYC Rome processors based on the 7nm Zen 2 architecture are not far from launch.
Thanks to STH, we now know one key feature of the upcoming processor which would absolutely crush the competition, if true. The 7nm Zen 2-based high-end CPU is expected to debut by the second half of 2019 and will be a completely different beast compared to its predecessors. The release notes found on AIDA64 details quality-of-life improvements along with physical CPU information display for AMD Castle Peak, Rome, updated JEDEC memory module manufacturers database and more.
ServerTheHome has concluded that AMD’s EPYC Rome processors would feature a higher number of PCI Express lanes than anticipated. We know that a single EPYC Rome processor would rock 128 PCIe Gen 4 lanes but this is particularly the dual socket servers that we are talking about. AMD EPYC Rome Processors are expected to rock up to 162 PCIe Gen 4 Lanes, Possibly More which is twice the amount of Intel’s Flagship Xeon Platinum 9200.
Only the Intel 4S and 8P solutions can offer more lanes with the specific PCIe lane count for each server solution mentioned below :
Another main feature of the new EPYC Rome processors includes the SCH (Integrated Server Controller Hub) which is mentioned as the standalone 14nm I/O die. In the previous processors, AMD had to share a lot of resources, including PCIe lanes by relying on low-speed 3rd party controllers.
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